INTRODUCTION
INTRODUCTION
Programmable logic array:-
A programmable logic array (PLA) is a programmable device used to implement combinational logic circuits. The PLA has a set of programmable AND gate planes, which link to a set of programmable OR gate planes, which can then be conditionally complemented to produce an output. This layout allows for a large number of logic functions to be synthesized in the sum of products (and sometimes product of sums) canonical forms.
One application of a PLA is to implement the control over a datapath. It defines various states in an instruction set, and produces the next state (by conditional branching). [eg. if the machine is in state 2, and will go to state 4 if the instruction contains an immediate field; then the PLA should define the actions of the control in state 2, will set the next state to be 4 if the instruction contains an immediate field, and will define the actions of the control in state 4]. Programmable Logic Arrays should correspond to a state diagram for the system.
Other commonly used programmable logic devices are PAL, CPLD and FPGA.
Note that the use of the word "Programmable" does not indicate that all PLAs are field-programmable; in fact many are mask-programmed during manufacture in the same manner as a mask ROM. This is particularly true of PLAs that are embedded in more complex and numerous integrated circuits such as microprocessors. PLAs that can be programmed after manufacture are called FPLA (Field-programmable PLA).
One way to design a combinational logic circuit it to get gates and connect them with wires. One disadvantage with this way of designing circuits is its lack of portability.
You can now get chips called PLA (programmable logic arrays) and "program" them to implement Boolean functions. I'll explain what it means to program a PLA.
Fortunately, a PLA is quite simple to learn, and produces nice neat circuits too.
History:-
Before PLAs were introduced, designers of digital logic circuits would use small-scale integration (SSI) components, such as those in the 7400 series TTL (transistor-transistor logic) family; the 7400 family included a variety of logic building blocks, such as gates (NOT, NAND, NOR, AND, OR), multiplexers (MUXes) and demultiplexers (DEMUXes), flip flops (D-type, JK, etc.) and others. One PAL device would typically replace dozens of such "discrete" logic packages, so the SSI business went into decline as the PAL business took off. PALs were used advantageously in many products, such as minicomputers, as documented in Tracy Kidder's best-selling book "The Soul of a New Machine."
PLAs were not the first commercial programmable logic devices; Signetics had been selling its field programmable logic array (FPLA) since 1975. These devices were completely unfamiliar to most circuit designers and were perceived to be too difficult to use. The FPLA had a relatively slow maximum operating speed (due to having both programmable-AND and programmable-OR arrays), was expensive, and had a poor reputation for testability. Another factor limiting the acceptance of the FPLA was the large package, a 600-mil (0.6", or 15.24 mm) wide 28-pin dual in-line package (DIP).
The project to create the PLA device was managed by John Birkner and the actual PAL circuit was designed by H. T. Chua. In a previous job, Mr. Birkner had developed a 16-bit processor using 80 standard logic devices. His experience with standard logic led him to believe that user programmable devices would be more attractive to users if the devices were designed to replace standard logic. This meant that the package sizes had to be more typical of the existing devices, and the speeds had to be improved. The PLA met these requirements and was a huge success and were "second sourced" by National Semiconductor, Texas Instruments, and Advanced Micro Devices.
Circuit Description :-
PLA means programmable logic array.
Logically, a PLA is a circuit that allows implementing Boolean functions in sum-of-product form. The typical implementation consists of input buffers for all inputs, the programmable AND-matrix followed by the programmable OR-matrix, and output buffers.
As shown in the applet, the input buffers provide both the original and the inverted values of each PLA input (here called A0, A1, A2, A3). The input lines run horizontally into the AND matrix, while the so-called product-term lines run vertically. Therefore, the size of the AND matrix is twice the number of inputs times the number of product-terms. A weak pullup-resitors ensures that the default value of all product-term signals is high.
Each place in the AND-matrix holds a small diode. Depending on the programming data, this diode is left unconnected, or connected to its input-line and product-line. While the unconnected diode will do nothing, the product-term line will be driven low by the connected diode whenever the corresponding input-line is low. This is the wired-AND operation: a product term will only remain high when none of the (connected!) input-lines is driven low. For example, the leftmost product-line (vertical) in the applet is connected via diodes to both A0 and inverted A3. Therefore, P0 = (!A3 & A0). A similar argument shows that the second product-line P1 = (A2 & A0).
The same structure is repeated in the output (OR-) matrix: the output-lines are driven by weak-pullup resistors, but can be driven low by product-term lines, whenever the corresponding diode is connected during programming.
For example, the upper output line Y4 is connected to both the first (leftmost) and second product-term lines, so that Y4 = P0 | P1, or Y4 = (!A3&A0) | (A2&A0). Similarly, Y0 = P6 | P7 | P8 = A2 | A1 | A0. The remaining product terms and outputs are unused, so that Y3 = Y2 = Y1 = 0.
The main advantage of the PLA structure is that a very compact and space-efficient realization is possible in NMOS technology. Small self-conducting (enhancement-mode) NMOS transistors are used for the pullup-resistors, while a depletion-mode NMOS transistor is placed at each location in the AND- and OR-matrices. The first-level metal mask decides whether to connect the transistors or not. The total-size of a PLA (excluding buffers) is calculated from twice the number of input lines plus the number of output terms times the number of product terms. For many functions, PLAs are much more compact that the discrete realization based on traditional gates. However, the pullup-transistors imply that a PLA draws a (rather large) static current. As low-power consumption is a primary concern in many current devices, PLAs are not as popular in current (CMOS-) technology integrated circuits as they were in the early era of VLSI.
Starting Out: ----
The first part of a PLA looks like:
Each variable is hooked to a wire, and to a wire with a NOT gate. So the top wire is x2 and the one just below is its negation, \x2.
Then there's x1 and just below it, its negation, \x1.
The next part is to draw a vertical wire with an AND gate. I've drawn 3 of them.
Let's try to implement a truth table with a PLA.
| x2 | x1 | x0 | z1 | z0 |
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 |
| 0 | 1 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 | 1 |
| 1 | 0 | 1 | 0 | 0 |
| 1 | 1 | 0 | 0 | 0 |
| 1 | 1 | 1 | 0 | 1 |
Each of the vertical lines with an AND gate corresponds to a minterm. For example, the first AND gate (on the left) is the minterm: \x2\x1x0.
The second AND gate (from the left) is the minterm: \x2x1x0.
The third AND gate (from the left) is the minterm: x2\x1\x0.
I've added a fourth AND gate which is the minterm: x2x1x0.
The first three minterms are used to implement z1. The third and fourth minterm are used to implement z0.
This is how the PLA looks after we have all four minterms.
Now we might complain. How is it possible to have a one input AND gate it can three inputs be hooked to the same wire to an AND gate. Isn't that invalid for combinational logic circuits.
That's true, it is invalid. However, the diagram is merely a simplification. I've drawn the each of AND gate with three input wires, which is what it is in reality (there is as many input wires as variables). For each connection (shown with a black dot), there's really a separate wire. We draw one wire just to make it look neat.
The vertical wires are called the AND plane. We often leave out the AND gates to make it even easier to draw.
We then add OR gates using horizontal wires, to connect the minterms together.
Again, a single wire into the OR gate is really 4 wires. We use the same simplification to make it easier to read.
The horizontal wires make up the OR plane.
This is how the PLA looks when we leave out the AND gates and the OR gates. It's not that the AND gates and OR gates aren't there---they are, but they've been left out to make the PLA even easier to draw.
Advantages of PLA:-
Programmable logic arrays (PLA's) :-
1.The ROM implementation of a function may become quite expensive for functions with a large number of variables, because all potential minterms of the function are implemented, whether or not they are needed. A programmable logic array (PLA) requires that only the minterms required for a function be implemented, and allows the implementation of several functions simultaneously. Moreover, the functions can be implemented directly from their minterm forms (although it is often possible to eliminate some of the minterms, further decreasing the cost of the PLA).
, this minterm is not included in the ``AND'' plane of the PLA. Note also that the PLA can implement a function in POS form directly, without reducing the function to minterm form. This often leads to opportunities for minimizing the area of a PLA. Also, a PLA can implement additional functions of the same set of variables simply by adding another logic gate to the ``OR'' plane. Thus the PLA is an efficient device for the implementation of several functions of the same set of variables. 
- Another application of a PLA is to implement the control over a datapath. It defines various states in an instruction set, and produces the next state (by conditional branching). [eg. if the machine is in state 2, and will go to state 4 if the instruction contains an immediate field; then the PLA should define the actions of the control in state 2, will set the next state to be 4 if the instruction contains an immediate field, and will define the actions of the control in state 4]. Programmable Logic Arrays should correspond to a state diagram for the system.
Abstract:-
A programmable logic array device in which programmable logic regions are arranged in groups of four is provided. The device includes direct connect conductors for carrying signals totally within one group of four regions as well as to certain adjacent programmable logic regions, local conductors for carrying signals within groups and among adjacent groups, and global conductors for carrying device-wide signals. Connections among the various conductors, and between conductors and programmable logic regions, are provided to optimize the connection resources by avoiding switched conductor paths wherever possible
References:-
· H. Fleisher et al., "The Writeable Personalized Chip," Computer Design
, Jun. 1970, pp. 59-66
· R. G. Shoup, "Programmable Cellular Logic Arrays," Ph.D. Dissertation, Carnegie-Mellon University (Pittsburgh), Mar. 26, 1970
· The Programmable Logic Data Book, Xilinx, Inc., 1994, pp. 2-7-2-46, 2-105-2-152
· Xilinx, Inc., "XC5000 FPGA Family: Product Review Sheet," Sep. 199
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