MOS capacitors

vIntroduction

vFlat Band diagram

vAccumulation

vExplanation of MOS capacitors

vMemory effect in MOS capacitors

v Non Ideal effects of MOS capacitor

vTheory of MOS capacitor

vBibliography

vReferences

INTRODUCTION

The MOS capacitor structure is a metal oxide semiconductor in which the “metal” plate is a heavily doped n⁺ - poly-silicon layer which behaves as a metal. The insulating layer is silicon dioxide and the other plate of the capacitor is the semiconductor layer which in our case is n-type silicon whose resistivity is 1-10 Ω-cm corresponding to a doping of 10¹⁵ cm^-3.

The capacitance of the MOS structure depends on the voltage (bias) on the gate. For the purposes of this discussion, we shall refer to the contact to the semiconductor as the body (B) while the poly-silicon is called the gate (G). Typically a voltage is applied to the gate while the body is grounded and the applied voltage is V_G but more accurately V_GB. The two (V_G & V_GB) will be used interchangeably in this document.

The MOS Capacitor structure

The energy band diagram of an n-MOS capacitor biased in inversion is shown in Figure .3. The oxide is modeled as a semiconductor with a very large bandgap and blocks any flow of carriers between the semiconductor and the gate metal. The band bending in the semiconductor is consistent with the presence of a depletion layer. At the semiconductor-oxide interface, the Fermi energy is close to the conduction band edge as expected when a high density of electrons is present. The semiconductor remains in thermal equilibrium even when a voltage is applied to the gate. The presence of an electric field does not automatically lead to a non-equilibrium condition, as was also the case for a p-n diode with zero bias.

Energy band diagram of an MOS structure biased in inversion .

In the next sections, we discuss the four modes of operation of an MOS structure: Flatband, Depletion, Inversion and Accumulation. Flatband conditions exist when no charge is present in the semiconductor so that the silicon energy band is flat. Initially we will assume that this occurs at zero gate bias. Later we will consider the actual flatband voltage in more detail. Surface depletion occurs when the holes in the substrate are pushed away by a positive gate voltage. A more positive voltage also attracts electrons (the minority carriers) to the surface, which form the so-called inversion layer. Under negative gate bias, one attracts holes from the p-type substrate to the surface, yielding accumulation.

Flatband Diagram Charges in an n-type Metal-Oxide-Semiconductor structure (p-type substrate) under accumulation, depletion and inversion conditions.

The flatband diagram is by far the easiest energy band diagram. The term flatband refers to fact that the energy band diagram of the semiconductor is flat, which implies that no charge exists in the semiconductor. The flatband diagram of an aluminum-silicon dioxide-silicon MOS structure is shown in Figure 6.2.4. Note that a voltage, VFB, must be applied to obtain this flat band diagram. Indicated on the figure is also the work function of the aluminum gate, M, the electron affinity of the oxide, oxide, and that of silicon, , as well as the bandgap energy of silicon, Eg. The bandgap energy of the oxide is quoted in the literature to be between 8 and 9 electron volt. The reader should also realize that the oxide is an amorphous material and the use of semiconductor parameters for such material can justifiably be questioned.

The flatband voltage is obtained when the applied gate voltage equals the workfunction difference between the gate metal and the semiconductor. If there is a fixed charge in the oxide and/or at the oxide-silicon interface, the expression for the flatband voltage must be modified accordingly.

Flatband energy diagram of a metal-oxide-semiconductor (MOS) structure consisting of an aluminum metal, silicon dioxide and silicon.

(a) Accumulation

Accumulation occurs when one applies a voltage less than the flatband voltage. The negative charge on the gate attracts holes from the substrate to the oxide-semiconductor interface. Only a small amount of band bending is needed to build up the accumulation charge so that almost all of the potential variation is within the oxide.

(b) Depletion

As a more positive voltage than the flatband voltage is applied, a negative charge builds up in the semiconductor. Initially this charge is due to the depletion of the semiconductor starting from the oxide-semiconductor interface. The depletion layer width further increases with increasing gate voltage.

(c) Inversion

As the potential across the semiconductor increases beyond twice the bulk potential, another type of negative charge emerges at the oxide-semiconductor interface: this charge is due to minority carriers, which form a so-called inversion layer. Explanation of Metal Oxide Semiconductor (MOS) Capacitor At the heart of all charge-coupled devices (CCDs) is a light-sensitive metal oxide semiconductor (MOS) capacitor, which has three components consisting of a metal electrode (or gate), an insulating film of silicon dioxide, and a silicon substrate. MOS capacitors are segregated into two classes of devices, one having a surface channel structure and the other having a buried channel design. It is the latter device that is used in the fabrication of modern CCDs, due to several advantages of the buried channel architecture. The MOS capacitor array is fabricated on a p-type silicon substrate (illustrated in Figure 1) in which the main charge carriers are positively charged electron "holes". Prior to the multi-step photolithography-driven CCD fabrication process, a polished silicon wafer is bombarded with boron ions to create channel stops that localize integrated charge within the confines of a single pixel gate set (not shown in Figure 1). After impregnation of the wafer with boron ions, a 10,000 angstrom layer of silicon dioxide is grown over the channel stops. The next step in the fabrication process is to create the buried channels by implanting phosphorous ions in areas that will eventually be covered by polysilicon gate electrodes. The n-type semiconductor formed by phosphorus contains negatively charged electrons as the primary charge carriers and forms a p n-type diode structure, which serves to localize potential wells deep beneath the silicon/silicon dioxide interface. The potential well illustrated in the central portion of Figure 1 is a schematic drawing of the diode structure. The primary function of the buried channel is to localize integrated electrons away from the silicon/silicon dioxide interface, where they can become trapped during charge transfer. By localizing charge deep within the p-type silicon substrate, transfer of charge occurs more efficiently with a minimum of residual charge remaining in the gate. After the buried channels are formed within the silicon substrate, a layer of silicon dioxide is thermally grown on the silicon wafer surface to provide an insulating base for the gate electrodes. Next, a phosphorous-doped layer of polycrystalline silicon (polysilicon) about 5,000 angstroms thick is grown on top of the oxide layer. This layer of polysilicon comprises the gate electrodes (see Figure 1) and is transparent to visible light, making it an ideal substance for use in CCDs. Although, the fabrication of a complete CCD takes additional steps, the basics of the MOS capacitor assembly have been completed at this point. When the capacitor is unbiased (does not have an applied voltage), electrons residing in the n-region of the device equilibrate to the lowest potential energy: Potential Energy = -|q| x  where q is the magnitude of charge density on an electron and  is the electrostatic potential. From this equation, it follows that electrons will localize where the electrostatic potential is greatest. A potential energy diagram for the n-region is presented in Figure 2, which illustrates where the electron ensemble is congregated within the capacitor (about 1 micron beneath the oxide layer). After a quantity of charge has been integrated by interaction with photons and a voltage is applied to the gate electrode with the silicon substrate held at ground potential, the electrostatic potential curve drawn in Figure 2 will tend to flatten at the peak. As the gate voltage is increased, the potential of electrons trapped in the buried channel rises in a linear manner. Memory effects in MOS capacitors with silicon rich oxide insulators To form crystalline Si dots embedded in SiO2, we have deposited thin films of silicon rich oxide (SRO) by plasma-enhanced chemical vapor deposition of SiH4 and O2. Then the materials were annealed in N2 ambient at temperatures between 950 and 1100 °C. Under such processing, the supersaturation of Si in the amorphous SRO film produces the formation of crystalline Si dots embedded in SiO2. The narrow dot size distributions, analyzed by transmission electron microscopy, are characterized by average grain radii and standard deviations down to about 1 nm. The memory function of such structures has been investigated in metal-oxidesemiconductor (MOS) capacitors with a SRO film sandwiched between two thin SiO2 layers as insulator and with an n+ polycrystalline silicon gate. The operations of write and storage are clearly detected by measurements of hysteresis in capacitance-voltage characteristics and they have been studied as a function of bias. Non-Ideal effects in MOS capacitors Non-ideal effects in MOS capacitors include fixed charge, mobile charge and charge in surface states. All three types of charge can be identified by performing a capacitance-voltage measurement. Fixed charge in the oxide simply shifts the measured curve. A positive fixed charge at the oxide-semiconductor interface shifts the flatband voltage by an amount which equals the charge divided by the oxide capacitance. The shift reduces linearly as one reduces the position of the charge relative to the gate electrode and becomes zero if the charge is located at the metal-oxide interface. A fixed charge is caused by ions which are incorporated in the oxide during growth or deposition. The flatband voltage shift due to mobile charge is described by the same equation as that due to fixed charge. However the measured curves differ since a positive gate voltage causes mobile charge to move away from the gate electrode, while a negative voltage attracts the charge towards the gate. This causes the curve to shift towards the applied voltage. One can recognize mobile charge by the hysteresis in the high frequency capacitance curve when sweeping the gate voltage back and forth. Sodium ions incorporated in the oxide of silicon MOS capacitors are known to yield mobile charge. It is because of the high sensitivity of MOS structures to a variety of impurities that the industry carefully controls the purity of the water and the chemicals used. Charge due to electrons occupying surface states also yields a shift in flatband voltage. However as the applied voltage is varied, the fermi energy at the oxide-semiconductor interface changes also and affects the occupancy of the surface states. The interface states cause the transition in the capacitance measurement to be less abrupt. The combination of the low frequency and high frequency capacitance allows to calculate the surface state density. This method provides the surface state density over a limited (but highly relevant) range of energies within the bandgap. Measurements on n-type and p-type capacitors at different temperatures provide the surface state density throughout the bandgap. Theory These are metal oxide semiconductor capacitors (MOSC), and the ece440 textbook has a description of what the capacitance vs. voltage curves should look like, as well as some of the information that can be determined from them. Here are some brief highlights: The capacitance of the oxide is given by: Cox = εA/d where: ε = dielectric constant of insulator = ε0εr A = area of the device d = distance between the plates (dielectric thickness) Under a particular bias polarity, a depletion layer will form in the silicon below the oxide, adding another capacitor in series with the oxide capacitor. The differential capacitance, Cd, of the semiconductor-space charge region is Cd = (dielectric constant of silicon)*(Area)/(Thickness of depletion region) The total capacitance is Ctot = (Cox * Cd)/(Cox+Cd) Here is a typical C-V curve for a MOS capacitor on a grounded n-type substrate with ±10V applied to the aluminum contact on top of the oxide. The flat regions corresponding to the oxide capacitance and the total capacitance at maximum depletion width are evident. It is possible to model the capacitors by separating the capacitance into center and edge effects. The equations are similar to those used for modeling the p-n junction capacitance. The total capacitance per area is Ctotal = P * Cedge + A * Carea, where P equals the perimeter and A equals the area. Note that the units of Cedge and Carea are pF/μm and pF/μm2, respectively. By using two of the capacitors, it is possible to solve for P and A. N-channel MOSFET (enhancement type): (a) 0 V gate bias, (b) positive gate bias. In Figure below (a) the MOS capacitor is placed between a pair of N-type diffusions in a P-type substrate. With no charge on the capacitor, no bias on the gate, the N-type diffusions, the source and drain, remain electrically isolated.

N-channel MOSFET (enhancement type): (a) Cross-section, (b) schematic symbol.

The MOSFET schematic symbol in Figure above (b) shows a “floating” gate, indicating no direct connection to the silicon substrate. The broken line from source to drain indicates that this device is off, not conducting, with zero bias on the gate.

REFRENCES

1. JACOB MILLMAN & HALKIAS, INTEGRATED ELECTRONICS: ANALOG & DIGITAL CIRCUIT SYSTEMS,

Mc GRAW HILL, 1991 EDITION, 41 PRINT, 2005.

2. ALLEN MOTHERSHED, ELECTRONIC DEVICES & CIRCUITS, AN INTRODUCTION, EEE PUBLICATIONS

3. A.P. MALVINO, ELCTRONIC PRINCIPLES, Mc GRAW HILL

4. DAVID A. BELL, ELECTRONIC DEVICES AND CIRCUITS, OXFORD.

Bibliography

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