Love-Electronics: Complex Programmable Logic Devices (CPLD)

Table of content:-

1. Acknowlegement

2. Abstract

$Description: C:\Users\sony\Desktop\arya\cpld\CD_CPLD_640.jpg$ 3. Introduction

4. CPLD (Complex programmable logic device)

a. MAX 7000 CPLD

I. The Macrocell

II. Parallel expander

b. The MAX II CPLD

7. Family of Xilinx

8. Implimentation Technology

8. Application

9. Problems

10. Future scopes

11. References

ACKNOWLEDGEMENT

I take this opportunity to present my votes of thanks to all those guidepost who really acted as lightening pillars to enlighten our way throughout this project that has led to successful and satisfactory completion of this study.

We are really grateful to our HOD Mr. ............. for providing us with an opportunity to undertake this project in this university and providing us with all the facilities. We are highly thankful to Mss. Rupendeep Kaur for her active support, valuable time and advice, whole-hearted guidance, sincere cooperation and pains-taking involvement during the study and in completing the assignment of preparing the said project within the time stipulated.

Lastly, We are thankful to all those, particularly the various friends , who have been instrumental in creating proper, healthy and conductive environment and including new and fresh innovative ideas for us during the project, their help, it would have been extremely difficult for us to prepare the project in a time bound framework.

$Description: C:\Users\sony\Desktop\arya\cpld\Ultra37000_CPLD_Overview_Pod.jpg$

ABSTRACT

The work describes the design and implementation of Complex Programmable Logic Devices (CPLDs) board for many digital applications in the educational and research field laboratory in the university. The objective of designed board is to implement the digital logic, which can be used for any digital application and take advantages of CPLDs features like reconfigurable architecture, high speed operation, pin locking, in-system programming (ISP) for digital system design. This CPLD board size is relatively compact; so it can be easily mounted. On board power supply and variable frequency oscillator improves functionality of overall board. The design includes some cost effective embedded control and communication interface to build digital application to work more efficiently in the market.

Introduction

(CPLDs) Complex programmable logic devices are integrated circuits (ICs) or chips that application designers configure to implement digital hardware such as mobile phones. CPLDs can handle significantly larger designs than simple programmable logic devices (SPLDs), but provide less logic than field programmable gate arrays (FPGAs). CPLDs contain several logic blocks, each of which includes eight to 16 macrocells. Because each logic block performs a specific function, all of the microcells within a logic block are fully connected. Depending upon the application, however, logic blocks may or may not be connected to one another.

COMPLEX PROGRAMMABLE LOGIC DVICES (CPLDs)

A CPLD (complex programmable logic device) consists basically of multiple SPLD arrays

with programmable interconnections, as illustrated in Figure I 1 . Although the way

CPLDs are internally organized varies with the manufacturer, Figure 11-10 represents a

generic CPLD. Here We have refer to each SPLD array in a CPLD as a LAB (logic array block).

Other designations are sometimes used, such as fimction block, logic block, or generic

block. The programmable interconnections are generally called the PIA (programmable in-

terconnect array) although some manufacturers, such as Xilinx, use the term AIM (ad-

vanced interconnect matrix) or a similar designation. The LABs and the interconnections

between LABs are programmed using software. A CPLD can be programmed for complex

logic functions based on the SOP structure of the individual LABs (actually SPLDs). In-

puts can be connected to any of the LABs, and their outputs can be interconnected to any

other LABs via the PIA.

Most programmable logic manufacturers make a series of CPLDs that range in density,

process technology, power consumption, supply voltage, and speed. Manufacturers usually

specify CPLD density in terms of macrocells or logic array blocks. Densities can range

from tens of macrocells to over 2000 macrocells in packages with up to several hundred

pins. As PLDs become more complex, maximum densities will increase. Most CPLDs are

reprogrammable and use EEPROM or SRAM process technology for the programmable

links. Power consumption can range from a few milliwatts to a few hundred milliwatts. DC

supply voltages are typically from 2.5 V to 5 V, depending on the specific device.

Several manufacturers, produces several CPLDs for example Altera, Xilinx, Lattice, and Cypress

ALTERA CPLDs

Altera produces several families of CPLDs including the MAX II, the MAX 3000, and the MAX 7000 family.


	$Description: C:\Users\sony\Desktop\arya\cpld\max7000-index.jpg$

MAX 7000 CPlD

The architecture of a CPLD is the way in which the internal elements are organized and arranged. The architecture of the MAX 7000 family is similar to the block diagram of a generic CPLD . It has the classic PAUGAL structure that produces SOP functions. The density ranges from 2 LABs to 16 LABs, depending on the particular device in the series, a LAB is roughly equivalent to one SPLD, and package sizes vary from 44 pins to 208 pins. The MAX 7000 series of CPLDs uses the EEPROM- based process technology. In-system programmable (lSP) versions use the JTAG standard interface.

a general block diagram of the Altera MAX 70UO series CPLD.

Four LABs are shown, but there can be up to sixteen, depending on the particular device in the series. Each of the four LABs consists of sixteen macrocells, and multiple LABs are linked together via the PIA, which is a programmable global (goes to all LABs) bus structure to which the general-purpose inputs. the I/Os. and the macrocells are connected.

$Description: C:\Users\sony\Desktop\arya\cpld\xcr3032xl.jpg$ The Macrocell :- The macrocell contains a small programmable AND array with five AND gates, an OR gate. a product-term selection matrix for connecting the AND gate outputs to the OR gate, and associated logic that can be programmed for input, combinational logic output, or registered output.Although based on the same concept, this macrocell differs somewhat from the macro- cell in relation to SPLDs because it contains a portion of the programmable AND array and a product-term selection matrix.

five AND gates feed product terms from the PIA into the product-term selection matrix. The product term from the bottom AND gate can be fed back inverted into the pro- grammable array as a shared expander for use by other macrocells. The parallel expander inputs allow borrowing of unused product terms from other macrocells to expand an SOP expression. The product-term selection matrix is an array of programmable connections that is used to connect selected outputs from the AND array and from the expander inputs to the OR gate.

Parallel Expanders:- Another way to increase the number of product terms for a macrocell is by using parallel expanders in which additional product terms are ORed with the terms generated by a macrocell instead of being combined in the AND array, as in the shared ex- pander. A given macrocell can borrow unused product terms from neighboring macrocells (up to five product terms from three other macrocells for the MAX 7000). The basic concept is illustrated in Figure where a simplified circuit that can produce two product terms borrows three additional product terms.

$Description: C:\Users\sony\Desktop\arya\cpld\max2-lp.jpg$ The MAX II CPLD

The architecture of the MAX II CPLD differs dramatically from the MAX 7000 family and is what Altera calls a "post-macrocell" CPLD. This device contains logic array blocks (LABs) each with multiple logic elements (LEs). An LE is the basic logic design unit and is analogous to the macrocelL .The programmable interconnects are arranged in a row and column arrangement running between the LABs, and input/output elements (lOEs) are oriented around the perimeter. The architecture of this family of CPLDs is similar to that of FPGAs. In fact, we could think of the MAX II as a low-density FPGA. A main difference between the MAX II CPLD and the classic SPLD-based CPLD is the way in which a logic function is developed.. An LUT is basically a type of memory that can be programmed to produce SOP functions,the MAX II CPLD has a row/column arrangement of interconnects instead of the channel-type interconnects found in most classic CPLDs.

These two approaches are contrasted in Figure and can be understood by comparing Figure 11-11 andFigure 11-17.

Most CPLDs use a non-volatile process technology for the programmable links. MAX II, however, uses a SRAM-based process technology that is volatile-all programmed logic is lost when power is turned off. The memory embedded on the chip stores the program data using non-volatile memory technology and reconfigures the CPLD on power up.

like Altera, Xilinx, makes a series of CPLDs that range in density , process technology, power consumption, supply voltage, and speed. Xilinx produces several families of CPLDs including Cool Runner II, Cool Runner XPLA3. and the XC9500. The XC9500 is similar in architecture to the Altera MAX 7000 CPLD family and exhibits the classic PAL/GAL structure.

Most CPLD contain the same type of programmable switches that are used in SPLds.Programing of switches may be accomplished using same techniques in which the chip is placed into a special- purpose programming unit.This programming method is rather unconvenient for larger CPLD for two reason

1.larger CPLD may have more than 200 pins on the chip package,and these pins are ofen fragile and easily bent.

2.To be programmed in a programming unit ,a socket is recqured to hold the chip.which is very expensive ,there cost sometime more than the cost of CPLD device itself.

For these reason ,CPLD device usually sipport ISP technique.A small connector is included on the PCB that houses the CPLd ,and a cable is connected between the connector and a computer system.The CPLd is programmed by transferring the programming information generated by CAD system through the cable,from the computer into CPLD .

Once the CPLD is programmed ,it retains the programmed state permanently ,even when the power supply for the chip is turned off.This property is called non-volatile programming,

FEATURES

• Advanced, High-speed, Electrically-erasable Programmable Logic Device

– Superset of 22V10

– Enhanced Logic Flexibility

– Backward Compatible with ATV750B/BL and ATV750/L

• Low-power Edge-sensing “L” Option with 1 mA Standby Current

• D- or T-type Flip-flop

• Product Term or Direct Input Pin Clocking for Flip-flop

• 7.5 ns Maximum Pin-to-pin Delay with 5V Operation

• Highest Density Programmable Logic Available in 24-pin and 28-pin Packages

– Advanced Electrically-erasable Technology

– Reprogrammable