THE EBERS-MOLL MODEL

THE EBERS-MOLL MODEL

The classic mathematical model for the bipolar junction transistor is the Ebers-Moll model formulated

by J. J. Ebers and J. L. Moll from Bell Laboratories in the early 1950s [5]. The Ebers-Moll

model provides an alternative view or representation of the equations developed in Sec. 5.2 and

is formulated using the same superposition of currents in the forward and reverse directions.

Forward Characteristics of the npn Transistor

The total current crossing the emitter-base junction in the forward direction in Fig. 5.3 is described

by Eq. (5.5) and can be rewritten as

in which the new parameter IES represents the reverse saturation current of the base-emitter diode.

The collector current in Eq. (5.1) can be rewritten in terms of IES as

The forward common-base current gain αF represents the fraction of the emitter current that

crosses the base and appears in the collector terminal

Reverse Characteristics of the npn Transistor

For the reverse direction depicted in Fig. 5.4, the current crossing the collector-base junction is

described by Eq. (5.11) and can be written as

The new parameter ICS represents the reverse saturation current of the base-emitter diode. The

emitter current from Eq. (5.9) can be rewritten in terms of ICS as

The reverse common-base current gain αR represents the fraction of the collector current that

crosses the base from the emitter terminal.

The Ebers-Moll Model for the npn Transistor

The full Ebers-Moll equations are obtained by combining Eqs. (5.20) to (5.23):

This model contains four parameters, IES, ICS, αF , and αR. From the definitions of IES and ICS,

we can obtain the important auxillary relation

which shows that there are only three independent parameters in the Ebers-Moll model, just as in

the transport formulation. The base current, given by iB = iE − iC, is

which is equivalent to the base current expression in Eq. (5.13).

The Ebers-Moll Model for the pnp Transistor

The equation set for the pnp transistor can be derived in a manner analogous to that of the npn

device, and such an analysis yields Eq. (5.27):

Equivalent Circuit Representations

for the Ebers-Moll Models

Equivalent circuit representations of the Ebers-Moll equations are useful as aids in hand analysis

and have been used as the model in many circuit simulation packages. The Ebers-Moll equivalent

circuits for the npn and pnp transistors are presented in Figs. 5.9(a) and 5.9(b), respectively.

Diode currents iF and iR are established by the voltages vBE and vBC applied to the base-emitter

and base-collector junctions, as represented by Eqs. (5.20) and (5.22), and the current-controlled

current sources represent the portions of the diode currents that are transported across the base

region of the devices.

Exercise: What are the values of αF , αR, IES, and ICS for the transistor in Example 5.1?

Show that αF IES = αRICS

Answers: 0.980, 0.500, 1.02 ?10−16 A, 2.00 ?10−16 A, 1.00 ?10−16 A = 1.00 ?10−16 A

Saturation

In the low resistance “on” state of a bipolar transistor, one finds that the voltage between the collector and emitter is less than the forward bias voltage of the base-emitter junction. Typically the “on” state voltage of a silicon BJT is 100 mV and the forward bias voltage is 700 mV. Therefore, the base-collector junction is also forward biased. Using the Ebers-Moll model, we can calculate the “on” voltage from:

Saturation also implies that a large amount of minority carrier charge is accumulated in the base region. As a transistor is switched from saturation to cut-off, this charge initially remains in the base and a collector current will remain until this charge is removed by recombination. This causes an additional delay before the transistor is turned off. Since the carrier lifetime can be significantly longer than the base transit time, the turn-off delay causes a large and undesirable asymmetry between turn-on and turn-off time. Saturation is therefore avoided in high-speed bipolar logic circuits. Two techniques are used to reduce the turn-off delay: 1) adding a Schottky diode in parallel to the base-collector junction and 2) using an emitter-coupled circuit configuration. Both approaches avoid biasing the transistor in the saturation mode. The Schottky diode clamps the base-collector voltage at a value, which is slightly lower than the turn-on voltage of the base-collector diode. An emitter-coupled circuit is biased with a current source, which can be designed such that the collector voltage cannot be less than the base voltage.

Example: Calculate the saturation voltage of a bipolar transistor biased with a base current of 1 mA and a collector current of 10 mA. Use a_R = 0.993 and a_F = 0.2.

Solution:

The saturation voltage equals:

Common Emitter Form of Ebers-Moll Model

This is a more useful form of the Ebers-Moll model for

circuit analysis. It can be derived from the common

base model.

DISADVANTAGE OF EBERS-MOLL MODEL

The Ebers moll model can only give a good prediction of terminal currents for moderate levels of injection i.e. base currents.

Model does not take into account high current and other non ideal effects.

A more elaborate bipolar device models the Gummel-Poon was therefore developed in 1970.

The Gummel Poon model is an extension of the Ebers Moll model.

It incorporate several secondary physical effects thatare ignored in the Ebers Moll e.g. high injection effects.

Although more accurate than the Ebers Moll model, many device parameters are required to model all the various physical effects.